FIG. 1 shows a conventional prior art phase-locked loop (PLL) circuit 10. It will be assumed for purposes of illustration that PLL 10 is designed to output a frequency of 50 MHz with an input reference clock (REFCLK) frequency of 5 MHz. It will also be assumed that the output frequency of voltage controlled oscillator (VCO) 11 decreases with an increased voltage applied to its control terminal.
In FIG. 1, a 5 MHz REFCLK signal is applied to a first input of a phase/frequency (P/F) detector 12. A nominal 50 MHz output signal at PLL output terminal 13 is divided by a divide-by-ten divider 14 to provide a 5 MHz feedback clock (FBCLK) signal to a second input of P/F detector 12.
P/F detector 12 supplies a pump down frequency (PDF) signal, via line 16, to a control terminal of a current pump 18 if it is detected by P/F detector 12 that the frequency of FBCLK is greater than the frequency of REFCLK. This causes current pump 18 to supply or sink, as appropriate, a current to its output line 20 so as to charge/discharge filter 22 and raise/lower the voltage at the control terminal of VCO 11 to lower the output frequency of VCO 11. In one type of VCO 11, an increased voltage at the input of VCO 11 will lower the output frequency of VCO 11. Accordingly, this resulting decrease in VCO 11 output frequency will cause the frequency of FBCLK to decrease until it is equal to the frequency of REFCLK. At this point, P/F detector 12 will stop supplying a PDF signal to current pump 18.
Conversely, if the frequency of FBCLK is less than that of REFCLK, P/F detector 12 will provide a pump up frequency (PUF) signal on line 26 to current pump 18. Current pump 18 then sinks current from line 20 to reduce the voltage on line 20 so as to increase the output frequency of VCO 11 and balance PLL 10.
As can be seen from the above description, PLL 10 will operate in such a manner as to make FBCLK track the frequency and phase of REFCLK. REFCLK is normally operated within a fixed frequency range for which PLL 10 was designed to track. If the frequency of REFCLK is increased beyond the designed range, the VCO 11 output frequency will increase in response, and the output frequency may exceed the maximum operating frequency of the feedback circuitry, shown as divider 14 in FIG. 1. The output of divider 14 may be incorrectly processed due to the excessive frequency, and the frequency of the FBCLK may be less than the frequency of the REFCLK signal, even as the VCO 11 attempts to increase its frequency further in response to a PUF signal on line 26 generated by P/F detector 12. Even if the frequency of REFCLK is then reduced to fall within the designed range, the frequency of FBCLK can remain lower than REFCLK, or stop switching altogether, as a result of the divider 14 being forced beyond its frequency limit. PLL 10 would then be locked in an undesirable state from which it cannot recover.
The lock-up state described above can also occur when first starting up the PLL 10 of FIG. 1, without exceeding the designed range for the REFCLK frequency. If, at power up, the output voltage VFILT on line 20 is initially near the ground potential, VCO 11 will initially begin operating at a very high frequency. If the maximum operating frequency of divider 14 is less than this initial VCO 11 output frequency, this could cause divider 14 to output a FBCLK signal having a frequency less than the frequency of REFCLK. The PLL 10 will then become locked in the previously described undesirable state.
In fact, any disturbance to the PLL 10 during power up or under quiescent conditions that causes the output frequency of VCO 11 to exceed the capabilities of the feedback circuit (e.g., divider 14) could result in the lock up condition.
As clocking speeds are becoming faster and faster, the VCO's used in PLL's to provide these high frequency signals must be designed so as to be capable of exceeding the desired PLL steady state clocking frequency to ensure that the VCO will be able to output the desired clocking frequency under any foreseeable conditions. To achieve maximum economy of performance, the feedback circuitry is operated near its maximum operating frequency, wherein the VCO's maximum frequency usually exceeds that of the feedback circuitry.
Additionally, manufacturers will want to design VCO's to be capable of providing clocking frequencies higher than currently needed in order to meet future needs.
Thus, although the extremely high speed, and possibly state of the art, circuits to be clocked by the output of a high frequency VCO in a PLL are intended to operate at the steady state high output frequency of the VCO, it is not likely that a feedback divider, such as divider 14 in FIG. 1, would be able to accurately process the maximum frequencies outputted by the VCO under all conditions. This could prevent a reliable FBCLK signal from being applied to P/F detector 12 and could delay or prevent the PLL from locking onto the REFCLK frequency.
It would be relatively expensive to provide divider 14 with state of the art components which are specially designed to process the maximum frequency output of the VCO.
What is needed is an economical high speed VCO circuit which avoids the above-identified drawbacks.